1. Field of the Invention
The invention relates to the field of floating gate devices, Classes 317/235R, 340/173R.
2. Prior Art
Memory devices, particularly metal-oxide-semiconductor (MOS) devices which include floating gates, have been utilized for the storage of information in the prior art. One such device is shown in U.S. Pat. No. 3,500,142; in this device the tunneling phenomena is utilized to charge a floating gate. Another device which utilizes avalanche injection for charging a floating gate (without the use of a second gate) is shown in U.S. Pat. No. 3,660,819. Other pertinent prior art is shown in U.S. Pat. Nos. 3,755,721; 3,825,946; 3,797,000. Memory arrays which employ such floating gate devices are disclosed in U.S. Pat. Nos. 3,728,695 and 3,744,036.
The present invention discloses a floating gate device which includes a second gate or control gate. The device employs two separate layers of polycrystalline silicon, one for the floating gate and the other for the control gate. The use of double level polycrystalline silicon in semiconductor devices is known in the prior art, for example, see IEEE spectrum, Sept. 1973, page 85, "New Product Applications."